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Espressif Systems /ESP32-P4 /LEDC /INT_ENA

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Interpret as INT_ENA

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIMER0_OVF_INT_ENA)TIMER0_OVF_INT_ENA 0 (TIMER1_OVF_INT_ENA)TIMER1_OVF_INT_ENA 0 (TIMER2_OVF_INT_ENA)TIMER2_OVF_INT_ENA 0 (TIMER3_OVF_INT_ENA)TIMER3_OVF_INT_ENA 0 (DUTY_CHNG_END_CH0_INT_ENA)DUTY_CHNG_END_CH0_INT_ENA 0 (DUTY_CHNG_END_CH1_INT_ENA)DUTY_CHNG_END_CH1_INT_ENA 0 (DUTY_CHNG_END_CH2_INT_ENA)DUTY_CHNG_END_CH2_INT_ENA 0 (DUTY_CHNG_END_CH3_INT_ENA)DUTY_CHNG_END_CH3_INT_ENA 0 (DUTY_CHNG_END_CH4_INT_ENA)DUTY_CHNG_END_CH4_INT_ENA 0 (DUTY_CHNG_END_CH5_INT_ENA)DUTY_CHNG_END_CH5_INT_ENA 0 (DUTY_CHNG_END_CH6_INT_ENA)DUTY_CHNG_END_CH6_INT_ENA 0 (DUTY_CHNG_END_CH7_INT_ENA)DUTY_CHNG_END_CH7_INT_ENA 0 (OVF_CNT_CH0_INT_ENA)OVF_CNT_CH0_INT_ENA 0 (OVF_CNT_CH1_INT_ENA)OVF_CNT_CH1_INT_ENA 0 (OVF_CNT_CH2_INT_ENA)OVF_CNT_CH2_INT_ENA 0 (OVF_CNT_CH3_INT_ENA)OVF_CNT_CH3_INT_ENA 0 (OVF_CNT_CH4_INT_ENA)OVF_CNT_CH4_INT_ENA 0 (OVF_CNT_CH5_INT_ENA)OVF_CNT_CH5_INT_ENA 0 (OVF_CNT_CH6_INT_ENA)OVF_CNT_CH6_INT_ENA 0 (OVF_CNT_CH7_INT_ENA)OVF_CNT_CH7_INT_ENA

Description

Interrupt enable register

Fields

TIMER0_OVF_INT_ENA

Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT.
TIMER1_OVF_INT_ENA

Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT.
TIMER2_OVF_INT_ENA

Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT.
TIMER3_OVF_INT_ENA

Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT.
DUTY_CHNG_END_CH0_INT_ENA

Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT.
DUTY_CHNG_END_CH1_INT_ENA

Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT.
DUTY_CHNG_END_CH2_INT_ENA

Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT.
DUTY_CHNG_END_CH3_INT_ENA

Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT.
DUTY_CHNG_END_CH4_INT_ENA

Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT.
DUTY_CHNG_END_CH5_INT_ENA

Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT.
DUTY_CHNG_END_CH6_INT_ENA

Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT.
DUTY_CHNG_END_CH7_INT_ENA

Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT.
OVF_CNT_CH0_INT_ENA

Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT.
OVF_CNT_CH1_INT_ENA

Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT.
OVF_CNT_CH2_INT_ENA

Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT.
OVF_CNT_CH3_INT_ENA

Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT.
OVF_CNT_CH4_INT_ENA

Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT.
OVF_CNT_CH5_INT_ENA

Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT.
OVF_CNT_CH6_INT_ENA

Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT.
OVF_CNT_CH7_INT_ENA

Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data